1. Field of the Invention
The present invention relates to a microcomputer including an input and output circuit having a plurality of operation modes, and performing processes under the control of a control program and, in particular, to an operation mode control circuit for controlling the operation mode of the input and output circuit, a microcomputer having the operation mode control circuit, and a control system including a the microcomputer and a watchdog timer.
2. Description of the Related Art
Microcomputer systems must reliably operate under adverse conditions with a monitoring function of a watchdog timer remaining effective. In the discussion that follows, the microcomputer refers to a typically available microcomputer, a microcomputer system, a semiconductor control apparatus such as a digital signal processor (DSP), or the like. In the system controlled by the microcomputer under the control of a control program, the microcomputer having an input and output circuit with a plurality of operation modes must reliably perform the operation mode of the input and output circuit set at the initialization of the microcomputer under the control of the control program. This is because input and output signals of the microcomputer greatly affect other devices within the microcomputer system that operate in response to the input and output signals of the microcomputer. As a result, the general operation of the microcomputer system is also affected.
There is a need for a circuit that reliably controls an operation mode once the operation mode is set in the input and output circuit contained in the microcomputer.
The conventional art relating to operation control of the input and output circuit of the microcomputer and a reliable operation of a microcomputer system employing a watchdog timer is discussed with reference to FIGS. 16 through 18.
A onboard vehicular LAN microcomputer system shown in FIG. 16 includes a microcomputer 602, a watchdog timer 605 that is an external LSI for monitoring the operation of the microcomputer 602 through a reset signal line 612 and P.RUN signal line 611, a power supply 603, an ROM 606, an input interface 601, a VCCII ON/OFF circuit 607 controlled by a sleep and wake up signal 610 from microcomputer 602, a VCCI 613, a VCCI 614, a low-voltage reset circuit 608, a communication LSI 609, a delay circuit 604, and multi-input AND gate 615.
The above onboard vehicular LAN microcomputer includes a watchdog timer (hereinafter simply referred to as a watchdog) 605 for monitoring the operation of the microcomputer 602. If the microcomputer 602 hangs for any reasons, the watchdog 605 detects an interruption of a signal from a monitoring signal generator in the microcomputer 602. The microcomputer 602 is then reset to prevent further erratic operation (Japanese Unexamined Patent Application Publication 5-32142).
A data processing apparatus shown in FIG. 17 is a single-chip microcomputer. The data processing apparatus includes a central processing unit (CPU) 701, a system controller (SYSC) 702, an interrupt controller (INT) 704, a read-only memory (ROM) 705, a random-access memory (RAM) 706, a timer 708, a serial communication interface (SCI) 707, first through eight input and output ports (IOP 1) 709 through (IOP 8) 716, a clock pulse generator (CPG) 703, internal data buses 717, and write request signals 718.
The data processing apparatus includes, in the single chip microcomputer, the SYSC 702 holding operation mode information. In an initialization process, the data processing apparatus automatically reads the information stored in the ROM 705, which is a non-volatile memory, and sets a control signal, not controlled by software, to the SYSC 702 having the operation mode information. The operation mode information stored in the SYSC 702 is not rewritten by software in the CPU 701 in operation subsequent to the initialization process. This arrangement prevents the operation mode from being erroneously rewritten. Such a system is disclosed in Japanese Unexamined Patent Application Publication No. 8-63445.
A microcomputer shown in FIG. 18 includes a CPU 801, a memory 802, internal buses 823, a protect control circuit 830 including a protect control register 804, address decoders 803, 811-814, logical elements 805-810, and a logical element 827, a clock generator circuit 819 having a control register 815, a peripheral unit A 820 having a control register 816, a peripheral unit B 821 having a control register 817, and a peripheral unit C 822 having a control register 818.
In the microcomputer, the protect control register 804 holds information as to whether to permit or inhibit data writing on the control registers 815-818 to write data therein on a per control register basis. If a write operation occurs, a control register to write is determined. The protect control circuit 830 controls a write signal based on the information of the protect control register 804. In this way, erroneous writing onto the control register due to a program malfunction is thus controlled. Such a technique is disclosed in Japanese Unexamined Patent Application Publication No. 8-235073, for example.